1. Field of the Invention
The present invention generally relates to a sample hold circuit and a method for sampling and holding a signal, and more particularly, to a sample hold circuit of an analog-to-digital converter (ADC) and a method for sampling and holding a signal.
2. Description of Related Art
Most of physical signals generated in daily life are analog signals. However, since a digital signal is easy to be edited, analyzed, stored and has a better anti-noise capability, in an actual application, the analog signal is generally converted into the digital signal through an analog-to-digital converter (ADC).
The ADC plays an important role in wireless communication systems and portable video image devices, and as the wireless communication systems and the portable video image devices are quickly developed, demand for a high conversion speed of the ADC is increased. In various types of ADC structures, a pipelined ADC can achieve features of high-speed input and fast processing. In a general ADC, a sample hold circuit is generally disposed at a front end thereof, which is used for holding the analog signal. Since a sampling time is very short, a sampling output is a series of discontinuous narrow pulses, so that certain time is required to digitalize each of the sampled narrow pulse signals. Therefore, between two samplings, the sampled analog signal is temporarily stored until a next sampling pulse is received, and such operation is referred to as “hold”. According to a basic principle of digital signal processing (i.e. the Nyquist sampling theorem), if the extracted analog signal is required to be accurately and truly rendered, a sampling frequency has to be higher than twice of a maximum frequency. Therefore, the conversion speed of the ADC is usually determined by an operation frequency of the sample hold circuit. As a signal processing speed of the ADC becomes higher, demand for the operation frequency of the corresponding sample hold circuit is accordingly increased. Therefore, to improve the operation frequency of the sample hold circuit to cope with an actual demand is an important subject.
FIG. 1 is a circuit diagram of a conventional sample hold circuit. Referring to FIG. 1, the sample hold circuit 100A includes switches SW1A-SW9A, capacitors C1A-C6A, and an operational amplifier 102A. The switches SW1A, SW2A, SW3A, SW6A, and SW9A are controlled by a first signal PH1 to be turned on when the sample hold circuit 100A is in a sampling state and to be turned off when the sample hold circuit 100A is in a holding state. Besides, the switches SW4A, SW5A, SW7A, and SW8A are controlled by a second signal PH2 to be turned off when the sample hold circuit 100A is in the sampling state and to be turned on when the sample hold circuit 100A is in the holding state. The voltage level of the first signal PH1 and the voltage level of the second signal PH2 are not high voltage levels at the same time. FIG. 2 illustrates the waveforms of the first signal PH1 and the second signal PH2. Referring to FIG. 2, the first signal PH1 and the second signal P112 are two rectangular wave signals reverse to each other. When the first signal PH1 is at a high voltage level, the second signal PH2 is at a low voltage level, and when the first signal PH1 is at the low voltage level, the second signal PH2 is at the high voltage level.
FIG. 3 is an equivalent circuit diagram of the sample hold circuit in FIG. 1 when the sample hold circuit is in the sampling state. Referring to FIG. 3, a short circuit is formed between the end T1 of the capacitor CIA and the end T2 of the capacitor C2A, and the voltage of the ends T1 and T2 is equal to a common voltage VCM, so that the charge provided by the waveform signal VIP and the ground signal VIN is stored in the capacitor C1A and the capacitor C2A. In addition, a short circuit is also formed between the output terminals VOP and VON, and because the voltage of the output terminals VOP and VON is equal to the common voltage VCM, no charge is stored in the capacitor C3A or the capacitor C4A. FIG. 4 is an equivalent circuit diagram of the sample hold circuit 100A in FIG. 1 when the sample hold circuit 100A is in the holding state. Referring to FIG. 4, the switches SW4A and SW5A connected with the capacitors C1A and C2A in parallel are turned on and accordingly respectively form a short circuit path between the two ends of the capacitor C1A and the capacitor C2A, so that the charge stored in the capacitors C1A and C2A when the sample hold circuit 100A is in the sampling state is transferred into the capacitors C3A, C4A, C5A, and C6A. The charge stored by the sample hold circuit 100A in the sampling state can be expressed as:C1A×(VIP−VCM )−C2A(VIN−VCM)  (1)
The charge stored by the sample hold circuit 100A in the holding state can be expressed as:C5A(VRP−VCM)−C6A(VRN−VCM)+C3A(VOP−VCM)−C4A(VON−VCM)  (2)
Based on the charge conservation law, the total charge stored by the sample hold circuit 100A in both states can be expressed as:C1A×(VIP−VCM)−C2A(VIN−VCM)=C5A(VRP−VCM)−C6A(VRN−VCM)+C3A(VOP−VCM)−C4A(VON−VCM)  (3)
Assuming the capacitance of each of the capacitors C1A-C6A is C, foregoing equation (3) is rewritten as:C×(VIP−VIN)=C×(VOP−VON)+C×(VRP−VRN)  (4)
It can be obtained from foregoing equation that (VOP−VON)=(VIP−VIN)−(VRP−VRN), wherein (VRP−VRN) is the direct current (DC) portion in the sampled analog signal, and (VOP−VON) is the alternating current (AC) portion in the sampled analog signal. Thus, the sample hold circuit 100A can eliminate the DC voltage (VRP−VRN) in the analog signal and provide an input signal without the DC voltage (VRP−VRN) at the output terminals VOP and VON.
FIG. 5 illustrates the variation of the voltage difference (VRP−VRN) between the two reference voltages VRP and VRN in FIG. 1 along a time axis. Referring to FIG. 1 and FIG. 5, while in the holding state, the conventional sample hold circuit 100A eliminates the DC signal in an analog signal sampled when the sample hold circuit 100A is in the sampling state by using the capacitors coupled to the input terminals of the operational amplifier 102A and the reference voltages, so as to output the AC portion of the sampled analog signal. Because the conventional sample hold circuit 100A completely eliminates the DC signal in the analog signal at a time in the holding state by using the reference voltages and the capacitors, the voltage levels of the reference voltages are quickly pulled down to a low level when the sample hold circuit 100A enters the holding state. When the operation rate of the ADC increases, the reference voltages cannot return to their original voltage levels in time, so that the DC signal in the analog signal cannot be completely eliminated. As a result, the ADC outputs an incorrect signal.